module rt_mod(
	input	aw_r_in,
	input	clkIn,
	input	[31:0]	rstIn,

	inout	[31:0]	busdata
);

always@(posedge clkIn)
begin
	if(aw_r_in == 1'b0)
	begin
		busdata <= rstIn;
	end
	else
	begin
		busdata <= 32'hz;
	end
end

endmodule